[Solved] How to alternate a SPDT with 2 clocks?

[johnyradio]

Hello

I've got a SPDT switch, S1.
And a clock C1. Every time the C1 goes High, it should drive S1 high (switch to position 1).
There's a slower clock, C2. When C2 goes High, it should drive S1 low (switch to position 2).
If C1 and C2 go high at the same time, C2 wins.

How to do this?

Thank You.

[pebe]

This uses one half of a CD4013 dual RS flip flop.

I hope you find it useful.

[johnyradio]

Seems the best solution i've seen!

What's the function of the RC? Delay?

Getting some errors in my simulator.

If i leave Qnext output open, I get:
Y4 : floating pin

If i ground Qnext, i get:
Transient error:
t=0
Y4 : grounded output

Any suggestions?
[img]http://i46.tinypic.com/qx6h55.jpg[/img]

[johnyradio]

here's the same circuit in a different simulator. No error messages, but the output trace stays low all the time. Any ideas? Thanks!

[img]http://i46.tinypic.com/33n8exh.jpg[/img]

[img]http://i47.tinypic.com/vfjndv.jpg[/img]

[johnyradio]

ok, i changed the cap from 1 farad to 1uf. Now getting rises on Q, but not as desired. I need Q to go high on the first fast-clock-C1 high (after the first slow-clock-C2 high), as described in the OP.

i have struggled with numerous truth tables, but just cannot get it! One of my truth tables suggests that driving both clocks through an AND gate may be the solution, but i can't get anything working with that either.

any ideas?

thank you!

[img]http://i46.tinypic.com/2vkkqh1.jpg[/img]

another issue with this one is, i'm seeing rises on the output on C1 falls, which is not desired. All changes should happen only on rising edges....

[pebe]

Hi,
In both your simulations you have made the wrong connection from C1. You have it connected to the 'S' (Set) input instead of the 'D' (data) input. The 'S' input should be grounded.

Basically, this is how it should work. A high on C1 takes 'D' high. A few nanoseconds later 'Clk' (Clock) goes high and copies the state of 'D' on to 'Q' so that goes high. The reason for the RC network is to ensure that 'D' has gone high before the clock pin activates.

You wanted C2 to override C1 so a high on C2 operates 'R' (Reset) and takes 'Q' low. According to the truth table in the data sheet, that action takes precedence over anything that happens with the 'D' and 'Clk' pins.

I didn't try the circuit out, so I hope it works OK for you.

[johnyradio]

Actually, I believe it's connected correctly. The Set pin is on top of the component. Here's the SR manual page from my simulator:
[img]http://i45.tinypic.com/2eex0d3.jpg[/img]

Thanks for the suggestion, tho.

One thing confuses me-- the man page says "When calculating transient, output voltage is always delayed by one calculation step." Not sure if that means ALL traces are equally delayed (and therefor in-sync with each other), or the output of the SR does not show it's real-world timing.

Anyone have any other ideas?

It's a tough problem, yet seems intuitively simple!

[johnyradio]

Please chime in over here if you like, we're discussing your circuit:
http://www.electronicspoint.com/alterna ... 175p2.html

Thanks!

[pebe]

I didn't see any pulse rate anywhere in your postings. But following your link to another forum I see your fast clock could be at up to 3MHz.

The delay time for the clock is obviously too long for that frequency, so I suggest you change the 10K to 1K and leave out the cap. The inherent input capacity of a few pf will probably give sufficient delay, but you may need to add a cap of up to 22pf.

[pebe]

Here is an alternative circuit that is not frequency dependent.
R2 is the collector pullup resistor.

[johnyradio]

Thanks, just saw this, will try it.

I see you're driving S1 with a transistor. Is a typical SR output insufficient?

Is it ok to use any common SR with your circuit?

Thanks

[pebe]

I had to put the transistor there to invert the output (see the truth table on the circuit). I could not use the -Q (Bar Q) output because both outputs go high when R ans S are both high.

I think you could use any RS flip flop. But if you use the 74*** series, you would need to reduce the supply voltage to 5V.

[johnyradio]

Beautiful. Didn't need the transistor for some reason. Thoughts?

Also, needed to convert the slow clock to a pulse (using RC + buffer). Did not give the desired result otherwise. Thoughts?

Interestingly (to me), changing the period of the source clock did not require changing the RC values-- the pulse ratio of the fast clock to the slow clock seemed to stay constant. Thoughts?

[img]http://i48.tinypic.com/6sb8dt.jpg[/img]

[img]http://i48.tinypic.com/91fn69.jpg[/img]

(the sine waves won't be used in my actual circuit, just used here to demonstrate the SPDT.)

[pebe]

[quote="johnyradio"]Beautiful. Didn't need the transistor for some reason. Thoughts?[/quote]
That was an inverter to get the output signal to the polarity you asked for in your original posting, ie.
C2 (slow) = S1 low, and
C1 (fast) = S1 High

[quote]Also, needed to convert the slow clock to a pulse (using RC + buffer). Did not give the desired result otherwise. Thoughts?[/quote]
Between pulses, the output takes up the last high state of R or S. So if you want S2 to win when C1 and C2 start together, Then make sure the pulse of S2 is longer.

[quote]Interestingly (to me), changing the period of the source clock did not require changing the RC values-- the pulse ratio of the fast clock to the slow clock seemed to stay constant. Thoughts?[/quote]
I cannot answer that without knowing the clock frequency and the value of the RC time constant.

[johnyradio]

All good. I just knew it had to be this simple. Thank you!