I have tried searching the forums and the web and couldn't find a good explanation for the following problem:
Problem:
A full adder is implemented using 9 NAND gates as shown. For the NAND gate used, an input change on A will propagate to X in 3.4ps. An input change on B will propagate to X in 4.1ps. Wire delay is neglected.Use 4 set of the full adder design shown to form the fastest possible 4 bit ripple-carry adder! A and B on the NAND gate can be chosen freely in the design. Given that there are registers before and after the adder, each of them driven by exactly the same clock! Delay to and from the registers are set to 0ns.What is the minimum clock cycle-time (maximum frequency), where the adder will work correctly for all input value changes on {A[3:0], B[3:0], CIN} to form the result {S[3:0], COUT}?
Solutions:
43.6 ps
42.9 ps
39.5 ps
38.8 ps
Problem solving method:
What I've done for a start is counting the worst-case gate delays for each process.
A[i],B[i] -> S[i] = 6 gate delays
A[i],B[i] -> Cout = 5 gate delays
Cin -> S[i] = 3 gate delays
Cin -> Cout = 2 Gate delays
Because the carry-out of one stage is the next's input I found that the total amount of gate delays is:
6 gate delays for generating the first signal (A,B -> Cout)
2 gate delays per intermediate stage (Cin -> Cout)
3 gate delays for producing the sum and carry-out outputs (Cin -> S)
Total gate delays: 12
So what I am asking is if my method is correct. And how you guys would recommend I proceed.
Best regards,
NB: I should note that I've never done anything like this before and my field of study is completely different.
