Hi,
I have being working on oscillators, when I was analyzing an issue I found that the oscillators is generating more frequency than tuned (5.8kHz instead 5kHZ).
This frequency is connected to IN1 / CLK1 of CPLD. Now I want to know, whether this effects the functionality of CPLD but it seems our module is functionally ok.
I have two questions here :
1.how the clock frequency of CPLD is determined, is it based on the required speed we need ??
2.What happens if the frequency exceeds the specified ??
Thanks in advance..